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10 часов Π½Π°Π·Π°Π΄

SoC Chip Lead (FPGA/SoC)

248Β 400$
Π€ΠΎΡ€ΠΌΠ°Ρ‚ Ρ€Π°Π±ΠΎΡ‚Ρ‹
onsite
Π’ΠΈΠΏ Ρ€Π°Π±ΠΎΡ‚Ρ‹
fulltime
Π“Ρ€Π΅ΠΉΠ΄
lead
Английский
b2
Π‘Ρ‚Ρ€Π°Π½Π°
US
Вакансия ΠΈΠ· списка Hirify.GlobalВакансия ΠΈΠ· Hirify Global, списка ΠΌΠ΅ΠΆΠ΄ΡƒΠ½Π°Ρ€ΠΎΠ΄Π½Ρ‹Ρ… tech-ΠΊΠΎΠΌΠΏΠ°Π½ΠΈΠΉ
Для мэтча ΠΈ ΠΎΡ‚ΠΊΠ»ΠΈΠΊΠ° Π½ΡƒΠΆΠ΅Π½ Plus

ΠœΡΡ‚Ρ‡ & Π‘ΠΎΠΏΡ€ΠΎΠ²ΠΎΠ΄

Для мэтча с этой вакансиСй Π½ΡƒΠΆΠ΅Π½ Plus

ОписаниС вакансии

ВСкст:
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TL;DR
SoC Chip Lead (FPGA/SoC): Architecting and delivering complex FPGA/SoC silicon from concept through tape-out and production with an accent on chiplet-based architectures, high-speed interfaces, system-level modeling, and IP integration. Focus on owning chip signoff, quantifying compute and memory tradeoffs, debugging power, timing, and signal-integrity issues, and applying agentic AI methodologies to accelerate design execution.

Location: San Jose, California, United States

Base pay: $248,400 annually, plus potential variable or incentive compensation and equity.

Company

hirify.global develops low-power programmable logic solutions, including FPGA, CPLD, and programmable power management devices.

What you will do

  • Lead development of FPGA and ASSP MCMs using 2.5D/3D advanced packaging and chiplet-based architectures.
  • Own chip tape-out, signoff, quality, and production release across multiple program generations.
  • Translate product requirements into SoC priorities, architectural tradeoffs, micro-architecture, and RTL decisions.
  • Lead cycle-approximate performance modeling and quantify compute, memory bandwidth, and interconnect tradeoffs.
  • Own system-level debug across floor planning, power distribution, clocking, timing closure, and signal and power integrity.
  • Define IP roadmaps, benchmark competing solutions, present technology roadmaps to executives, and apply agentic AI methodologies to accelerate design execution.

Requirements

  • BS, MS, or PhD in Electrical or Computer Engineering.
  • 20+ years of FPGA/SoC design experience and a track record delivering programs from concept through tape-out and production.
  • Expertise in SystemVerilog, synthesis, static timing analysis, high-speed interfaces, system interconnects, processor subsystems, and chiplet-based architectures.
  • Experience with system-level functional and performance modeling, RTL correlation, emulation-based pre-silicon validation, verification, and system validation.
  • Experience defining DFx methodology, including scan, BIST, and manufacturing test from IP through chip level.
  • Ability to lead geographically distributed, cross-functional engineering teams and present to executive leadership. Successful background and reference checks and proof of the right to work in the United States are required.

Culture & Benefits

  • Results-oriented, team-first environment across international locations.
  • Healthcare and retirement plans may be included in the benefits package.
  • Paid time off and other competitive benefits are available.
  • Eligible for variable or incentive compensation and equity.

Π‘ΡƒΠ΄ΡŒΡ‚Π΅ остороТны: Ссли Ρ€Π°Π±ΠΎΡ‚ΠΎΠ΄Π°Ρ‚Π΅Π»ΡŒ просит Π²ΠΎΠΉΡ‚ΠΈ Π² ΠΈΡ… систСму, ΠΈΡΠΏΠΎΠ»ΡŒΠ·ΡƒΡ iCloud/Google, ΠΏΡ€ΠΈΡΠ»Π°Ρ‚ΡŒ ΠΊΠΎΠ΄/ΠΏΠ°Ρ€ΠΎΠ»ΡŒ, Π·Π°ΠΏΡƒΡΡ‚ΠΈΡ‚ΡŒ ΠΊΠΎΠ΄/ПО, Π½Π΅ Π΄Π΅Π»Π°ΠΉΡ‚Π΅ этого - это мошСнники. ΠžΠ±ΡΠ·Π°Ρ‚Π΅Π»ΡŒΠ½ΠΎ ΠΆΠΌΠΈΡ‚Π΅ "ΠŸΠΎΠΆΠ°Π»ΠΎΠ²Π°Ρ‚ΡŒΡΡ" ΠΈΠ»ΠΈ ΠΏΠΈΡˆΠΈΡ‚Π΅ Π² ΠΏΠΎΠ΄Π΄Π΅Ρ€ΠΆΠΊΡƒ. ΠŸΠΎΠ΄Ρ€ΠΎΠ±Π½Π΅Π΅ Π² Π³Π°ΠΉΠ΄Π΅ β†’