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10 часов назад

Advanced Packaging Design Verification & Physical Validation Engineer

Формат работы
onsite
Тип работы
fulltime
Грейд
middle
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Advanced Packaging Design Verification & Physical Validation Engineer (DRC/LVS/DFM): Executing physical verification for complex, multi-die advanced packaging architectures with an accent on design quality, shift-left validation, and workflow automation. Focus on debugging violation reports, developing validation scripts and methodologies, and improving package design execution before final tape-out.

Location: Burlington, VT, United States

Expected base pay range: $0–$0 per annum, plus eligibility for bonus and equity plans.

Company

hirify.global develops semiconductor solutions and advanced packaging technologies for enterprise, cloud, AI, and carrier data infrastructure.

What you will do

  • Own and execute package floor-planning checks, DRC, LVS, and DFM flows for complex multi-die packaging architectures.
  • Implement shift-left validation checkpoints to identify design errors earlier and reduce late-stage layout iterations.
  • Identify verification pipeline bottlenecks and develop automation scripts, custom methodologies, and enhanced design kits.
  • Collaborate with package architects, physical layout designers, tool vendors, foundries, and external suppliers to resolve violations and interpret design rules.
  • Document verification processes and train other team members on established methodologies.

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • 3+ years of experience in semiconductor design or manufacturing roles.
  • Experience in quality improvement, design validation, or process validation.
  • Strong scripting skills in TCL, Python, Perl, or Skill for verification automation and data analysis.
  • Strong analytical, communication, and collaboration skills for work across R&D and supply partners.
  • Eligibility to access export-controlled technology and software under U.S. export control laws may be required.

Nice to have

  • Experience running and debugging DRC, LVS, and DFM on silicon or packaging layouts.
  • Experience with Siemens Calibre, Synopsys IC Validator, or Cadence Pegasus.
  • Knowledge of 2.5D/3D ICs, chiplets, CoWoS, silicon interposers, or high-density fan-out packaging.

Culture & Benefits

  • Collaborative R&D environment focused on advanced packaging innovation.
  • Bonus and equity plans, including a new-hire equity grant and annual equity refreshers.
  • Employee stock purchase plan with a two-year lookback.
  • Family support programs and mental health resources.
  • Recognition and service awards.

Hiring process

  • Interviews assess individual experience, problem-solving, and communication skills.
  • AI tools, transcription applications, automated answer generators, and note-taking bots are not permitted during interviews.

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