Research-Hardware Codesign Engineer (AI)

TL;DR

Research-Hardware Codesign Engineer (AI): Shapes the numerics, architecture, and technology bets of future hirify.global silicon in collaboration with Research and Hardware teams. Focus on debugging performance gaps, quantifying system architecture tradeoffs, and prototyping novel numeric RTL for advanced AI workloads.

Location: Hybrid, 3 days/week onsite in San Francisco, CA. Relocation assistance is available.

Salary: $230K – $460K + Offers Equity

Company

hirify.global is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity.

What you will do

• Build and maintain the roofline simulator to track evolving AI workloads.
• Analyze and quantify the impact of system architecture decisions for technology pathfinding.
• Debug performance gaps between performance simulation and real measurements, clearly communicating root cause.
• Write emulation kernels for low-precision numerics and lossy compression schemes.
• Prototype numerics modules by pushing RTL through synthesis, and occasionally own an RTL module end-to-end.
• Proactively pull in new ML workloads, prototype them with rooflines, and drive initial evaluation of new opportunities or risks.

Requirements

• Exceptional track record of high-quality technical output and a bias for shipping a prototype now.
• Strong proficiency in Python, and C++ or Rust, with an intuition for clean extensibility.
• Experience writing Triton, CUDA, or similar, and an understanding of tensor ops mapping to functional units.
• Working knowledge of PyTorch or JAX; experience in large ML codebases is a plus.
• Practical understanding of floating point numerics, ML tradeoffs of reduced precision, and current state of the art in model quantization.
• Deep understanding of transformer models, their rooflines, and tradeoffs of sharded training/inference in large-scale ML systems.
• English: B2 required

Nice to have

• Experience writing RTL (especially for floating point logic) and understanding of PPA tradeoffs.
• Strong cross-functional communication across ML researchers and hardware engineers.

Culture & Benefits

• Develops silicon and system-level solutions designed for advanced AI workloads.
• Works closely with software and research partners to co-design hardware integrated with AI models.
• Creates custom design tools and methodologies that accelerate innovation optimized specifically for AI.
• Committed to providing reasonable accommodations to applicants with disabilities.
• Dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity.
• Focuses on pushing the boundaries of AI systems while deploying them safely.