Pic Design Engineer (Ai)

TL;DR

PIC Design Engineer (AI): Responsible for the design and layout of very large-scale Silicon Photonic ICs (PICs) that interface directly with co-designed ASICs with an accent on opto-electronic performance, signal integrity (SI) & power integrity (PI). Focus on optimizing layout flows and adding to existing software base for automated design and verification.

Location: Santa Clara, CA

Salary: $185,000.00 - $225,000.00

Company

hirify.global’s Photonic Fabric™ is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions.

What you will do

• Contribute to the design and layout of very large-scale Silicon Photonic ICs (PICs) that interface directly with co-designed ASICs.
• Contribute to PIC delivery, all the way from floor-planning and top-level block placement to micro-architecture, optical & electrical routing, and back-end DRC and LVS verification.
• Work in conjunction with broader analog, digital and packaging teams to drive PIC physical design in accordance with product requirements related to opto-electronic performance, signal integrity (SI) & power integrity (PI).
• Optimize layout flows and add to existing software base for automated design and verification.

Requirements

• Good grasp of fundamental photonics concepts and engineering design principles.
• Experience with Silicon Photonics Process Design Kits and related best practices in the layout of photonic devices, sub-systems and full PICs.
• Experience with physical design packages (Cadence, Siemens Mentor, Klayout or similar), including layout automation within these tools using SKILL, Python or similar.
• Experience with layout verification tools for DRC, ERC and LVS (Calibre, Pegasus or similar).
• PhD in engineering or physics with concentration/experience in integrated photonics.

Culture & Benefits

• Great benefits (health, vision, dental and life insurance).
• Collaborative and continuous learning work environment.
• Chance to work with smart and dedicated people engaged in developing the next generation architecture for high performance computing.