TL;DR
Senior Physical Design Engineer (Iot Hardware): Taking ownership of shaping next-generation low-power Wi-Fi SoCs and driving RTL-to-GDSII implementation. Focus on timing closure, signal integrity, and power optimization, collaborating with world-class engineers and leading foundry partners to deliver high-quality designs.
Location: Stockholm, Sweden | Tampere, Finland | Bristol, UK
Company
hirify.global is inspired and supported to develop in professional and informal working environment.
What you will do
- Convert RTL-design into a physical layout (GDSII).
- Perform floorplanning, placement, clock tree synthesis (CTS), and routing.
- Apply low-power design techniques (e.g., multi-Vt cells, power gating, clock gating).
- Ensure compliance with power budgets for battery-operated Wi-Fi devices.
- Achieve timing closure across multiple corners and modes (MCMM) and work on setup/hold fixes, signal integrity, and clock skew management.
- Work closely with RTL designers, verification engineers, and package engineers, and collaborate with foundry for process-specific optimizations.
Requirements
- M.Sc in Electronics Engineering or equivalent
- Strong foundation in digital design principles, CMOS technology, and VLSI design.
- Expertise in RTL-to-GDSII flow, including floorplanning, placement, clock tree synthesis (CTS), and routing.
- Expertise with signal integrity, IR drop analysis, and electromigration checks.
- Hands-on experience with low-power design techniques like Multi-Vt cells, power gating, clock gating, multiple voltage domains.
- Proficiency in EDA tools and scripting skills for automation (Tcl, Perl, Python, or Shell).
Culture & Benefits
- Competitive salary with short- and long-term incentive plan
- Flexible working hours
- Medical insurance
- Family-friendly policies, insurances, and benefits
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