Senior Physical Design Engineer

TL;DR

Senior Physical Design Engineer (ASIC/Semiconductor): Developing physical design and methodology for next-generation high-performance processor chips with an accent on block-level PNR for advanced CMOS process nodes. Focus on synthesis, place and route, timing analysis, and EMIR sign-off checks to ensure robust database readiness.

Location: Must be based in Austin, TX (On-site)

Salary: $95,200–$140,860 per annum

Company

hirify.global is a global leader in semiconductor solutions, providing essential data infrastructure technology for cloud, AI, and enterprise architectures.

What you will do

• Execute block-level PNR for advanced CMOS process nodes.
• Run RTL code through synthesis and PNR tools to create physical chip views.
• Perform timing analysis and EMIR analysis to verify power grid integrity.
• Review completed runs for errors and implement optimizations.
• Collaborate with a global team on design methodology and workflow triage.

Requirements

• Must be eligible to access export-controlled information under U.S. law.
• Bachelor’s degree in Computer Science, Electrical Engineering, or related field.
• Experience in physical design with a focus on block-level PNR for advanced CMOS nodes (7nm, 5nm, or below).
• Proficiency with industry-standard EDA tools such as Cadence Genus/Innovus or Synopsys Design/IC/Fusion Compiler.
• Must be able to work on-site in Austin, TX.

Nice to have

• Working knowledge of static timing analysis tools like Tempus or PrimeTime.
• Experience with EM/IR-Drop/Crosstalk analysis tools like Voltus or PrimeRail.
• Familiarity with physical and formal verification tools such as Calibre, LEC, or Formality.

Culture & Benefits

• Comprehensive financial well-being programs including an employee stock purchase plan.
• Robust family support and mental health resources.
• Commitment to professional growth through mentorship and learning opportunities.
• Recognition and service awards for employee contributions.