Senior Principal Engineer (Hardware Application Engineering) (Signal Integrity & Power Integrity)

TL;DR

Senior Principal Engineer (Hardware Application Engineering) (Signal Integrity & Power Integrity): Own signal integrity (SI) and power integrity (PI) for customer platforms built on hirify.global Ethernet Switch and UALink silicon, from first prototype through mass-production qualification, with an accent on end-to-end SI/PI lifecycle, post-silicon extraction & simulation, and compliance/tuning guidance. Focus on translating lab and field telemetry into actionable layout/stack-up fixes, PDN architecture recommendations, and SerDes tuning methodologies for next-generation 112G/224G PAM4 and emerging 448G systems.

Location: Santa Clara, CA

Salary: $177,820 - $266,400 per annum (USD)

Company

hirify.global develops semiconductor solutions for data infrastructure across enterprise, cloud, and AI.

What you will do

• Serve as the senior SI/PI technical authority for customer platforms from early channel definition through mass-production qualification.
• Define and maintain layout/routing guidelines for high-speed SerDes channels, PDN, and sensitive analog interfaces; drive adoption with customers and ODMs.
• Run post-silicon channel extraction, full-channel simulation, and what-if analysis; recommend targeted layout/stack-up fixes to improve margins.
• Lead compliance testing and lab characterization (BER/SER, eye margins, jitter, return loss, crosstalk) and convert results into SerDes tuning guidance.
• Perform PI simulations (PDN impedance, IR drop, decoupling, transient response, droop) and guide robust PDN architectures for high-current ASICs.
• Provide hands-on lab debug support and deliver SI/PI training; feed learnings back into hirify.global silicon, packaging, and platform engineering teams.

Requirements

• PhD, Master’s, or Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 15+ years of experience in hardware design, development, and validation of high-speed networking or compute systems.
• 10+ years of focused SI/PI experience on high-speed SerDes platforms (25G NRZ through 112G/224G PAM4).
• Proven SI lifecycle expertise: channel modeling/budgeting, layout & stack-up guidelines, post-layout extraction & simulation, design-fix recommendations, and compliance/tuning guidance.
• Strong PI capability to independently run/review PDN simulations and translate results into customer guidance.
• Fluency with leading SI/PI EDA toolchains (e.g., Ansys HFSS/SIwave, Cadence Sigrity/Clarity/PowerSI) and strong hands-on lab debug skills (VNAs, BERTs, oscilloscopes, TDR, jitter analyzers, compliance test kits).

Culture & Benefits

• Employee stock purchase plan with a 2-year look back.
• Family support programs to balance work and home life.
• Robust mental health resources and recognition/service awards.
• Travel to customer sites, ODMs, and labs as needed, typically project-driven rather than continuous.

Hiring process

• Interviews evaluate individual experience, thought process, and communication skills in real time.
• Use of AI tools during interviews is not permitted and may result in disqualification.
• Role may require eligibility to access export-controlled information under U.S. export control laws.