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7 часов назад

IP Design Verification Engineer

Формат работы
hybrid
Тип работы
fulltime
Грейд
middle
Английский
c1
Страна
Mexico
Вакансия из списка Hirify.GlobalВакансия из Hirify RU Global, списка компаний с восточно-европейскими корнями
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Описание вакансии

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TL;DR

IP Design Verification Engineer (Memory Controller): Ensuring the functional integrity of memory controller IP designs for high-performance computing solutions with an accent on SystemVerilog/Python-based verification environments and microarchitecture validation. Focus on debugging complex design issues, enhancing verification methodologies, and collaborating with cross-functional teams to drive technical excellence in the memory ecosystem.

Location: Must be based in Guadalajara, Mexico (Hybrid work model)

Company

hirify.global is a global leader in computing innovation, delivering high-performance Xeon-based solutions and custom x86 products for data centers, web services, and AI-accelerated systems.

What you will do

  • Develop and execute comprehensive IP verification plans, test benches, and environments.
  • Define and run system simulation models to identify and resolve design bugs.
  • Perform root cause analysis and debug design issues in presilicon environments.
  • Collaborate with architects, RTL developers, and physical design teams to enhance verification approaches.
  • Document test plans and lead technical reviews to ensure design alignment.
  • Maintain and refine functional verification infrastructure, methodologies, and tools.

Requirements

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science.
  • Minimum 2+ years of experience in SystemVerilog and Python for verification.
  • Strong understanding of microarchitecture fundamentals and IP validation tools.
  • Advanced English proficiency is required for all candidates.
  • Must have unrestricted, permanent right to work in Mexico (no visa sponsorship).
  • Experience with power/performance validation and formal verification techniques.

Nice to have

  • Experience with memory protocols such as LPDDR5/6, HBM, or DDR5.
  • Knowledge of RTL design.
  • Advanced degree (Master's or PhD) with 2+ years of relevant experience.
  • Proven ability to drive technical reviews and group problem-solving sessions.

Culture & Benefits

  • Hybrid work model allowing flexibility between on-site and off-site work.
  • Opportunity to influence cutting-edge memory controller IP for world-class computing.
  • Collaborative environment working with multidisciplinary teams on complex architectural features.
  • Commitment to ethical hiring practices and RBA compliance.

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