Senior Physical Design Application Engineer

TL;DR

Senior Physical Design Application Engineer (ASIC/Physical Design): Provide technical support to hirify.global Foundry Services customers on PDKs, digital reference flows, and design signoff methodologies with an accent on Cadence tool suites and ASIC tape-out success. Focus on validating design reference flows, improving design kit quality and documentation, and developing/optimizing digital implementation flows for advanced CMOS processes.

Location: US, Arizona, Phoenix (Hybrid: split time between on-site at assigned hirify.global site and off-site)

Salary: $122,440.00–$232,190.00 USD (annual)

Company

hirify.global Foundry delivers silicon process and packaging technology leadership and design services for the AI era.

What you will do

• Provide customer technical support for PDKs, digital reference flows, and digital design signoff methodologies.
• Deliver ASIC/digital tool/flow/methodology solutions using Cadence tool suites to resolve customer issues and enable successful tape-outs.
• Drive quality improvements in design kits and documentation via ASIC design reference flow validation and documentation review.
• Create application notes, technical content, and training presentations for customers and internal teams.
• Develop and optimize digital design implementation flows for advanced CMOS processes, including hierarchical and multi-voltage domain approaches.
• Build and maintain QA regression frameworks for design validation.

Requirements

• US Citizenship required
• Ability to obtain a US Government Security Clearance
• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a STEM-related field
• 4+ years of experience with advanced CMOS processes (22nm and below)
• 3+ years of experience in ASIC physical design implementation and/or ASIC design signoff (SoC/ASIC)
• 3+ years of experience with scripting languages (Python, Perl, Tcl, or shell scripting)

Nice to have

• Active US Government Security Clearance (Secret level minimum)
• Postgraduate degree in a relevant STEM field
• Customer-facing experience in technical support roles
• Experience with 7nm and below process technology
• Hands-on Cadence EDA experience across full-chip integration, synthesis, APR, static timing analysis, layout verification, and reliability verification
• Proficiency with Cadence tools/flows (Innovus, Tempus, TempusECO, Pegasus, Voltus) and/or Synopsys tools (Fusion Compiler, PrimeTime, Prime ECO, ICV)

Culture & Benefits

• Hybrid work model: split time between on-site at the assigned hirify.global site and off-site.
• Total compensation package includes competitive pay, stock bonuses, and benefits (health, retirement, vacation).
• Opportunity to work with cutting-edge digital design technologies for foundry services.
• Direct customer engagement and technical leadership in advanced semiconductor design.
• Professional development in digital design methodologies and foundry services.

Hiring process

• Recruiter shares location-specific compensation details during the hiring process.
• Interviews evaluate technical fit for Cadence-based ASIC physical design and design signoff support.
• Security clearance requirements are part of eligibility.