Principal Engineer - Digital IC Design

TL;DR

Principal Engineer - Digital IC Design (DSP/Semiconductor): Designing and implementing advanced high-speed digital subsystems for PAM/Coherent DSPs using cutting-edge CMOS technology with an accent on micro-architecture, RTL development, and static timing closure. Focus on leading design efforts from specification to prototype bring-up, ensuring high quality and performance in complex SoC environments.

Location: Pavia, Italy (Onsite)

Company

hirify.global is a global leader in semiconductor solutions, providing essential data infrastructure technology for cloud, AI, enterprise, and carrier architectures.

What you will do

• Define subsystem architecture, micro-architecture, and register specifications for complex SoCs.
• Develop efficient RTL using Verilog/SystemVerilog and oversee synthesis.
• Collaborate with cross-functional teams including architecture, verification, physical design, and DFT to ensure timing closure and quality.
• Conduct formal equivalence, Lint, and cross-clock domain (CDC) analysis.
• Provide technical guidance and mentorship to junior engineering team members.
• Assist in design automation and EDA flow enhancements for chip development.

Requirements

• MS or PhD in Electrical Engineering or related field.
• Minimum 10 years of professional experience in digital IC design.
• Proven expertise in RTL coding, DFT design, and static timing analysis (STA).
• Deep experience in all stages of the ASIC design flow.
• Ability to work in a high-speed (>1 GHz) development environment.
• Eligible to access technology subject to U.S. export control laws.

Nice to have

• Experience with high-performance DSP product design.
• Proficiency in scripting languages such as Python, Perl, or Tcl.
• Experience with Unix shell environments.

Culture & Benefits

• Competitive compensation package and comprehensive benefits.
• Collaborative, transparent, and inclusive work environment.
• Resources for continuous professional growth and career development.
• Exposure to cutting-edge semiconductor innovation and industry-leading technologies.

Hiring process

• Interviews are conducted to evaluate individual experience and technical communication skills.
• Strict policy: Use of AI tools (ChatGPT, Copilot, etc.) during interviews is prohibited and results in disqualification.