Principal Engineer (Digital IC Design)

TL;DR

Principal Engineer (Digital IC Design): Developing next-generation high-speed PAM/Coherent DSPs and PHY designs for data infrastructure using cutting-edge CMOS technology with an accent on architecture definition, RTL development, and physical implementation. Focus on solving complex digital design challenges including synthesis, static timing closure, and DFT to ensure high-performance silicon quality.

Location: Onsite in Pavia, Italy

Company

hirify.global is a global semiconductor leader providing essential data infrastructure solutions across cloud, AI, enterprise, and carrier markets.

What you will do

• Define micro-architecture and register specifications for complex SoCs.
• Develop efficient RTL using Verilog and SystemVerilog.
• Execute synthesis, static timing analysis, and formal verification.
• Design, debug, and implement DFT structures for ICs and blocks.
• Collaborate with architecture, verification, floorplanning, and backend teams.
• Mentor junior engineers and contribute to EDA flow automation.

Requirements

• MS or PhD in EE or related technical field with 10+ years of professional experience.
• Fluent in RTL coding design techniques, including DFT, resets, LEC, and Lint.
• Expertise in synthesis, static-timing closure, gate-level simulations, and multi-clock design.
• Proficiency in ASIC design flow from specification through to prototype bring-up.
• Experience with high-speed DSP product design (greater than 1 GHz).
• Strong scripting skills in Python, Perl, or Tcl.

Nice to have

• Deep knowledge of UNIX shell environments.
• Previous experience with cross-clock domain (CDC) analysis.

Culture & Benefits

• Competitive compensation and benefits package.
• Environment focused on shared collaboration, transparency, and inclusivity.
• Opportunity to work on industry-leading, high-performance semiconductor solutions.
• Resources and tools provided to support professional growth and development.