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ΠΎΠ±Π½ΠΎΠ²Π»Π΅Π½ΠΎ 14 Π΄Π½Π΅ΠΉ Π½Π°Π·Π°Π΄

Senior Technical Staff Engineer - Architect (Memory Interconnect)

107Β 000 - 226Β 000$
Π€ΠΎΡ€ΠΌΠ°Ρ‚ Ρ€Π°Π±ΠΎΡ‚Ρ‹
onsite
Π’ΠΈΠΏ Ρ€Π°Π±ΠΎΡ‚Ρ‹
fulltime
Π“Ρ€Π΅ΠΉΠ΄
senior
Английский
b2
Π‘Ρ‚Ρ€Π°Π½Π°
Canada
РСлокация
Canada
Вакансия ΠΈΠ· списка Hirify.GlobalВакансия ΠΈΠ· Hirify Global, списка ΠΌΠ΅ΠΆΠ΄ΡƒΠ½Π°Ρ€ΠΎΠ΄Π½Ρ‹Ρ… tech-ΠΊΠΎΠΌΠΏΠ°Π½ΠΈΠΉ
Для мэтча ΠΈ ΠΎΡ‚ΠΊΠ»ΠΈΠΊΠ° Π½ΡƒΠΆΠ΅Π½ Plus

ΠœΡΡ‚Ρ‡ & Π‘ΠΎΠΏΡ€ΠΎΠ²ΠΎΠ΄

Для мэтча с этой вакансиСй Π½ΡƒΠΆΠ΅Π½ Plus

ОписаниС вакансии

ВСкст:
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TL;DR

Senior Technical Staff Engineer - Architect (Memory Interconnect): Leading cross-functional teams to deliver high-performance IP integrations into FPGA products with an accent on meeting market & customer requirements. Focus on architecture & implementation for Analog, ASIC & FPGA design development, integration, and deployment for high performance parallel interconnect.

Location: Toronto, Canada

Salary: $107,000 - $226,000

Company

hirify.global Technology Inc. is a leading semiconductor company empowering innovation to enhance the human experience.

What you will do

  • Lead cross-functional teams to deliver high-performance IP integrations into hirify.global FPGA products.
  • Work on architecture & implementation for Analog, ASIC & FPGA design development, integration, and deployment for high performance parallel interconnect.
  • Understand customer use cases and the role of IP in overall system architecture.
  • Collaborate with other architects, designers, and back-end implementation teams.
  • Lead and manage other engineers in the team.

Requirements

  • MSc or higher in EE, CS, CE or other applicable disciplines.
  • 12+ years of industrial experience.
  • Proven experience in ASIC & FPGA IP development, integration, and deployment, including all stages of development from Synthesis, constraint management, place & route, floorplanning, timing closure, CDC/RDC.
  • Proven ability to work cross-functionally with other architects, designers, and back-end implementation teams.
  • Knowledge and experience with Synopsys & Cadence ASIC flows.

Nice to have

  • Knowledge and experience with system-level performance modeling in TLM/SystemC/Other.
  • Experience in technical leadership and people management.
  • Scripting for EDA in Perl, Python, Tcl.

Culture & Benefits

  • Competitive base pay, restricted stock units, and quarterly bonus payments.
  • Health benefits that begin day one, retirement savings plans, and an industry leading IESPP program with a 6-month look back feature.
  • Employee development and values-based decision making.

Π‘ΡƒΠ΄ΡŒΡ‚Π΅ остороТны: Ссли вас просят Π²ΠΎΠΉΡ‚ΠΈ Π² iCloud/Google, ΠΏΡ€ΠΈΡΠ»Π°Ρ‚ΡŒ ΠΊΠΎΠ΄/ΠΏΠ°Ρ€ΠΎΠ»ΡŒ, Π·Π°ΠΏΡƒΡΡ‚ΠΈΡ‚ΡŒ ΠΊΠΎΠ΄/ПО, Π½Π΅ Π΄Π΅Π»Π°ΠΉΡ‚Π΅ этого - это мошСнники. ΠžΠ±ΡΠ·Π°Ρ‚Π΅Π»ΡŒΠ½ΠΎ ΠΆΠΌΠΈΡ‚Π΅ "ΠŸΠΎΠΆΠ°Π»ΠΎΠ²Π°Ρ‚ΡŒΡΡ" ΠΈΠ»ΠΈ ΠΏΠΈΡˆΠΈΡ‚Π΅ Π² ΠΏΠΎΠ΄Π΄Π΅Ρ€ΠΆΠΊΡƒ. ΠŸΠΎΠ΄Ρ€ΠΎΠ±Π½Π΅Π΅ Π² Π³Π°ΠΉΠ΄Π΅ β†’